All articles tagged with #risc v
Bit-Brick Cluster K1 is a versatile 4-slot RISC-V cluster board designed for edge computing, AI, and embedded applications, supporting up to four SSOM-K1 modules with high-performance features, extensive I/O options, and software support for various operating systems, available for around $125 without modules.
Linux 6.18 introduces significant IOMMU driver updates for Intel, AMD, Apple, and RISC-V systems, including fixes, support for new hardware features, and improved compatibility, enhancing system security and performance.
Linus Torvalds criticized a late submission of RISC-V support patches for Linux, calling the code 'garbage' and emphasizing the importance of timely, high-quality contributions, which delays the inclusion of these patches until Linux 6.18 at the earliest.
Linus Torvalds publicly criticized a late and poor-quality RISC-V code contribution from a Google engineer, calling it 'garbage' and warning against future late submissions and low-quality code, emphasizing the importance of early and clean pull requests for the Linux kernel.
Linus Torvalds rejected the RISC-V architecture changes for Linux 6.17 due to late submission and poor code quality, calling some of the proposed code 'garbage' and emphasizing the need for early, high-quality pull requests for the next release, Linux 6.18.
Oxmiq Labs, founded by Raja Koduri, has launched a startup that offers a licensing model for core GPU and AI chip technology based on open-source RISC-V, aiming to reduce chip development costs by up to 90% and make advanced computing more accessible for various applications and companies, including those in India.
NVIDIA announced that they will bring their CUDA software to RISC-V processors, expanding support beyond x86_64, AArch64, and previously IBM POWER, reflecting the growing interest in RISC-V for data centers. The Linux driver stack is portable, and similar support has been seen with AMD's ROCm on RISC-V and LoongArch processors.
A developer has created a 160-core RISC V supercluster on a single M.2 board using low-speed CH32V003 cores, demonstrating its potential with a raymarcher demo, despite communication bottlenecks over PCIe.
Silicon Valley chip developer Rivos Inc. has raised over $250 million, with Matrix Capital Management as the largest investor, to support its first product aimed at meeting the needs of artificial intelligence. The company is targeting AI users who don't require the most powerful chips, aiming to compete with Nvidia Corp. by offering cost-effective solutions using open-standard RISC-V design. The funding will be used to pilot produce chips using Taiwan Semiconductor Manufacturing Co.’s 3NE process technology, with investors including Intel Capital and MediaTek Inc. Rivos's CEO, Puneet Kumar, previously part of the team at P.A. Semi Inc., started the company in 2021 after a legal dispute with Apple, which has now been settled.
The U.S.-born chip technology RISC-V has become crucial to China's ambitions, sparking a new debate in Washington about potential restrictions on exporting the technology to China. RISC-V, which provides a common language for designing processors found in various devices, has become a central tool for Chinese companies and government institutions aiming to match U.S. semiconductor prowess. Lawmakers are considering extending restrictions to prevent U.S. citizens from aiding China on RISC-V, amid concerns about the technology being used to undermine export controls and advance the geopolitical interests of the Chinese Communist Party.
Tim Alex Jacobs has created what he calls the "smallest and worst" USB MIDI synthesizer using the CH32V003, a 32-bit RISC-V microcontroller. Despite no competition for the title, Jacobs proudly showcases his creation, highlighting the affordability and uniqueness of the device.
A low-cost CH32V003 MCU, lacking temperature measurement functionality, can be improvised to include a temperature sensor by measuring the drift between two internal clocks and using it to calibrate a temperature graph. By utilizing the automatic wake-up unit (AWU) and accessing the LSI clock source indirectly, a temperature plot was obtained, although the absolute accuracy of this method may vary per MCU. This crude temperature measurement solution could be sufficient for basic applications.
Android smartphones and other devices may switch to RISC-V-based processors in the coming years, as Google improves support for the open-source architecture. RISC-V, developed by the University of California, Berkeley, is gaining momentum as an alternative to ARM, which currently dominates the mobile device space. RISC-V's royalty-free and open-source nature appeals to smartphone brands, as it eliminates the need for costly licensing fees. Qualcomm is already developing a RISC-V-based processor for Wear OS smartwatches, and other chipset brands like MediaTek and Samsung may follow suit. This shift could lead to more affordable smartphones for consumers in the future.
Google has announced that the development environment and emulation for RISC-V Android are in place, indicating that RISC-V phones will soon be hitting the market. This could lead to a proliferation of powerful RISC-V computing, similar to the trend seen with inexpensive ARM single board computers. However, it is expected that these devices will still come with proprietary peripherals and closed source blobs.
Google has announced its plans to provide developer tools for RISC-V architecture in Android by 2024. The company has already developed the "Cuttlefish" virtual device emulator for Android OS development, allowing developers to work on a RISC-V Android build without the need for an individual RISC-V device. Google aims to have emulators available publicly with a full feature set by 2024 to test applications for various device form factors. The post also confirms that a Qualcomm smartwatch will be the first RISC-V Android device on the market.