Intel's upcoming 'Panther Lake' microarchitecture, based on the 18A process node, is set for a deep dive presentation on October 9, with a full launch expected at CES 2026. The product marks Intel's significant investment in advanced manufacturing, with initial limited shipments of 18A wafers already underway. The lineup will include low-power and high-performance SKUs, featuring various core configurations and integrated Xe3 graphics, with final specifications to be announced at the launch.
AMD has unveiled its new Zen 5 microarchitecture, powering the Ryzen AI 300 series for mobile and Ryzen 9000 series for desktops. The Zen 5 architecture offers significant improvements in performance and efficiency, including a 16% increase in instructions per cycle (IPC) over Zen 4. The Ryzen AI 300 series features the XDNA 2 NPU for enhanced AI capabilities, while the Ryzen 9000 series supports the AM5 platform and introduces new overclocking features. Both series aim to deliver better performance and power efficiency across various computing tasks.
AMD has initiated the enablement of its Zen5 microarchitecture in the GNU Compiler Collection (GCC) with the introduction of patches, ahead of the expected Zen5 product launch later this year. The Zen5 architecture is anticipated to feature new AVX instructions such as AVXVNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI, which were previously absent in AMD products. This development coincides with Intel's work on the Clearwater Forest and Panther Lake CPU series, not expected to launch this year. The initial patches also indicate that Zen5 will support the same instruction set across its entire family of products, with potential power-efficient variants. However, there are unresolved questions regarding the availability of LLVM/Clang compilers for Zen5, as patches for this compiler are yet to be seen.
