AMD is shifting from SERDES-based die-to-die interconnects to a 'Sea-of-Wires' fan-out approach in Zen 6 CPUs, inspired by Strix Halo APUs, which reduces power and latency while increasing bandwidth, marking a significant upgrade in interconnect technology.
The Apple Vision Pro's logic board, revealed during a disassembly by iFixit, shows the M2 chipset and R1 co-processor, with speculation that the R1 may employ a chiplet design due to distinctive lines on its packaging. This approach could allow Apple to integrate various nodes for CPU, GPU, and NPU on a single die, potentially reducing development times and costs. While not everyone is convinced, the possibility of Apple adopting a chiplet design for future custom SoCs remains intriguing.
Rumored details about Intel's 15th Gen Arrow Lake CPUs include up to 40 cores, a 30% performance boost, and a 2nm (20A) process with backside power delivery and Nanoribbon transistors. The desktop chips will feature a chiplet design with four tiles, including Compute or CPU, Graphics, SoC, and I/O. The iGPU is expected to have gaming performance on par with low-end dGPUs. Arrow Lake-S is expected to arrive in late 2024.